R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 14

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

6.4
6.5
6.6
6.7
6.8
6.9
6.10 Usage Note......................................................................................................................... 195
Section 7 User Break Controller (UBC)............................................................197
7.1
7.2
7.3
Rev. 3.00 Sep. 28, 2009 Page xii of xxx
REJ09B0313-0300
6.3.7
6.3.8
6.3.9
Interrupt Sources................................................................................................................ 165
6.4.1
6.4.2
6.4.3
6.4.4
6.4.5
6.4.6
Interrupt Exception Handling Vector Table and Priority................................................... 168
Operation ........................................................................................................................... 178
6.6.1
6.6.2
Interrupt Response Time.................................................................................................... 182
Register Banks ................................................................................................................... 188
6.8.1
6.8.2
6.8.3
6.8.4
6.8.5
Data Transfer with Interrupt Request Signals .................................................................... 193
6.9.1
6.9.2
6.10.1 Timing to Clear an Interrupt Source ..................................................................... 195
6.10.2 Timing of IRQOUT Negation............................................................................... 195
Features.............................................................................................................................. 197
Input/Output Pin ................................................................................................................ 199
Register Descriptions ......................................................................................................... 200
7.3.1
7.3.2
7.3.3
7.3.4
7.3.5
7.3.6
PINT Interrupt Request Register (PIRR) .............................................................. 161
Bank Control Register (IBCR).............................................................................. 162
Bank Number Register (IBNR) ............................................................................ 163
NMI Interrupt........................................................................................................ 165
User Break Interrupt ............................................................................................. 165
H-UDI Interrupt .................................................................................................... 165
IRQ Interrupts....................................................................................................... 165
PINT Interrupts..................................................................................................... 166
On-Chip Peripheral Module Interrupts ................................................................. 167
Interrupt Operation Sequence ............................................................................... 178
Stack after Interrupt Exception Handling ............................................................. 181
Banked Register and Input/Output of Banks ........................................................ 189
Bank Save and Restore Operations....................................................................... 189
Save and Restore Operations after Saving to All Banks....................................... 191
Register Bank Exception ...................................................................................... 192
Register Bank Error Exception Handling ............................................................. 192
Handling Interrupt Request Signals as Sources for CPU Interrupt but
Not DMAC Activating.......................................................................................... 194
Handling Interrupt Request Signals as Sources for Activating DMAC but
Not CPU Interrupt................................................................................................. 194
Break Address Register (BAR)............................................................................. 201
Break Address Mask Register (BAMR) ............................................................... 202
Break Data Register (BDR) .................................................................................. 203
Break Data Mask Register (BDMR)..................................................................... 204
Break Bus Cycle Register (BBR) ......................................................................... 205
Break Control Register (BRCR) ........................................................................... 207