R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1447

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

28.2.10 Deep Standby Control Register (DSCTR)
DSCTR is an 8-bit readable/writable register that selects whether to retain the contents of the
corresponding area of the on-chip RAM (for data retention) in deep standby mode. Only byte
access is valid.
When the RRAMKP3 to 0 bits are set to 1, the contents of the corresponding area of the on-chip
RAM (for data retention) are retained in deep standby mode. When these bits are cleared to 0, the
contents of the corresponding area of the on-chip RAM (for data retention) are not retained in
deep standby mode.
Note: When writing to this register, see section 28.4, Usage Notes.
Bit
7 to 4
3
2
Bit Name
⎯
RRAMKP3
RRAMKP2
Initial value:
Initial
Value
All 0
0
0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R/W
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
On-Chip RAM Storage Area 3 (corresponding area of
on-chip RAM (for data retention): page 3*)
0: The contents of the corresponding on-chip RAM
1: The contents of the corresponding on-chip RAM
On-Chip RAM Storage Area 2 (corresponding area of
on-chip RAM (for data retention): page 2*)
0: The contents of the corresponding on-chip RAM
1: The contents of the corresponding on-chip RAM
R
5
0
-
(for data retention) area are not retained in deep
standby mode.
(for data retention) area are retained in deep
standby mode.
(for data retention) area are not retained in deep
standby mode.
(for data retention) area are retained in deep
standby mode.
R
4
0
-
RRAM
R/W
KP3
3
0
Rev. 3.00 Sep. 28, 2009 Page 1415 of 1650
RRAM
R/W
KP2
2
0
RRAM
R/W
KP1
1
0
Section 28 Power-Down Modes
RRAM
R/W
KP0
0
0
REJ09B0313-0300