R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1456

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Section 28 Power-Down Modes
28.3.2
(1)
The LSI switches from a program execution state to software standby mode by executing the
SLEEP instruction when the STBY bit and DEEP bit in STBCR are 1 and 0 respectively. In
software standby mode, not only the CPU but also the clock and on-chip peripheral modules halt.
The clock output from the CKIO pin also stops in clock modes 0, 1 and 3.
The contents of the CPU and cache registers remain unchanged. Some registers of on-chip
peripheral modules are, however, initialized. As for the states of on-chip peripheral module
registers in software standby mode, see section 30.3, Register States in Each Operating Mode.
The CPU takes one cycle to finish writing to STBCR, and then executes processing for the next
instruction. However, it takes one or more cycles to actually write. Therefore, execute a SLEEP
instruction after reading STBCR to have the values written to STBCR by the CPU to be definitely
reflected in the SLEEP instruction.
The procedure for switching to software standby mode is as follows:
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Set the WDT's timer counter (WTCNT) to 0 and the CKS[2:0] bits in WTCSR to appropriate
3. After setting the STBY and DEEP bits in STBCR to 1 and 0 respectively, read STBCR. Then,
Rev. 3.00 Sep. 28, 2009 Page 1424 of 1650
REJ09B0313-0300
values to secure the specified oscillation settling time.
execute a SLEEP instruction.
Transition to Software Standby Mode
Software Standby Mode

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