R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1460

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 28 Power-Down Modes
28.3.4
(1)
The LSI switches from a program execution state to deep standby mode by executing the SLEEP
instruction when the STBY bit and DEEP bit in STBCR are set to 1. In deep standby mode, not
only the CPU, clocks, and on-chip peripheral modules but also power supply is turned off
excluding the on-chip RAM (for data retention) retaining area specified by the RRAMKP3 to
RRAMKP0 bits in DSCTR and RTC. This can significantly reduce power consumption.
Therefore, data in the registers of the CPU, cache, and on-chip peripheral modules are not
retained. Pin state values immediately before the transition to deep standby mode are retained.
The CPU takes one cycle to finish writing to DSCTR, and then executes processing for the next
instruction. However, it actually takes one or more cycles to write. Therefore, execute a SLEEP
instruction after reading DSCTR to reflect the values written to DSCTR by the CPU in the SLEEP
instruction without fail.
The procedure for switching to deep standby mode is as follows. Figure 28.2 also shows its
flowchart.
1. To ensure that data is actually retained in deep standby mode by the on-chip RAM (for data
2. Set the RRAMKP3 to RRAMKP0 bits in DSCTR for the corresponding on-chip RAM (for
3. To cancel deep standby mode by an interrupt, set to 1 the bit in DSSSR corresponding to the
4. Execute read and write of an arbitrary but the same address for each page in the retaining on-
5. Set the STBY and DEEP bits in the STBCR register to 1.
6. Read out the DSFR register after clearing the flag in the DSFR register. Then execute the
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retention), set H'09 to DSRTR.
data retention) area that must be retained. Transfer the programs to be retained to the specified
areas of the on-chip RAM (for data retention).
pin to be used for cancellation. In this case, also set the input signal detection mode (using
interrupt control registers 0 and 1 (ICR0 and ICR1) of the interrupt controller (INTC)) for the
pin used for cancellation. In the case of deep standby mode, only rising- or falling-edge
detection is valid. (Low-level detection or both-edge detection of the IRQ signal cannot be
used to cancel deep standby mode.)
chip RAM (for data retention) area. When this is not executed, data last written may not be
written to the on-chip RAM (for data retention). If there is a write to the on-chip RAM (for
data retention) after this time, execute this processing after the last write to the on-chip RAM
(for data retention).
SLEEP instruction.
Transition to Deep Standby Mode
Deep Standby Mode