R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1465

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 28 Power-Down Modes
When deep standby mode is canceled by interrupts (NMI or IRQ) or a manual reset, the deep
standby cancel source flag register (DSFR) can be used to confirm which interrupt has canceled
the mode.
Pins retain the state immediately before the transition to deep standby mode. However, in system
activation through the external bus, the retention of the states of the external bus control pins is
cancelled so that programs can be fetched after cancellation of deep standby mode. Other pins,
after cancellation of deep standby mode, continue to retain the pin states until writing 0 to the
IOKEEP bit in DSFR from the same bit. In system activation from the on-chip RAM (for data
retention), after cancellation of deep standby mode, both the external bus control pins and other
pins continues to retain the pin states until writing 0 to the IOKEEP bit in DSFR from the same
bit. Reconfiguration of peripheral functions is required to return to the previous state of deep
standby mode. Peripheral functions include all functions such as CPG, INTC, BSC, I/O ports,
PFC, and peripheral modules. After the reconfiguration, the retention of the pin state can be
canceled and the LSI returns to the state prior to the transition to deep standby mode by reading 1
from the IOKEEP bit in DSFR and then writing 0 to it.
(4)
Notes on Transition to Deep Standby Mode
After deep standby mode is specified, interrupts other than those set as cancel sources in the deep
standby cancel source select register are masked. If multiple interrupts are set as cancel sources in
the deep standby cancel source select register and more than one of these cancel sources are input,
multiple cancel source flags are set.
In addition, if a SLEEP instruction to initiate the transition to deep standby mode coincides with
an NMI or IRQ interrupt, or with a manual reset, acceptance of the interrupt may cause
cancellation of deep standby mode.
Rev. 3.00 Sep. 28, 2009 Page 1433 of 1650
REJ09B0313-0300