R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 147
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Table 4.5
Bit
7 to 5
4
3
2 to 0
Setting
00
01
10
11
Bit Name
⎯
IFC
⎯
PFC[2:0]
Output
Output
Output
Output off (Hi-Z)
Normal
Operation
CKOEN[1:0] Settings
Initial
Value
All 0
0
0
011
Release of Bus
Mastership
Output off (Hi-Z)
Output
Output
Output off (Hi-Z)
R/W
R
R/W
R
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Internal Clock Frequency Division Ratio
This bit specifies the frequency division ratio of the
internal clock with respect to the output frequency of
PLL circuit.
0: × 1 time
1: × 1/2 time
Reserved
This bit is always read as 0. The write value should
always be 0.
These bits specify the frequency division ratio of the
peripheral clock with respect to the output frequency
of PLL circuit.
000: Reserved (setting prohibited)
001: Reserved (setting prohibited)
010: Reserved (setting prohibited)
011: × 1/4 time
100: × 1/6 time
101: × 1/8 time
110: × 1/12 time
Peripheral Clock Frequency Division Ratio
Software Standby
Mode
Output off (Hi-Z)
Low-level output
Output (unstable
clock output)
Output off (Hi-Z)
Rev. 3.00 Sep. 28, 2009 Page 115 of 1650
Section 4 Clock Pulse Generator (CPG)
Deep Standby
Mode
Low-level or high-level
output
Low-level or high-level
output
Low-level or high-level
output
Output off (Hi-Z)
REJ09B0313-0300
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