R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1492

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 30 List of Registers
Rev. 3.00 Sep. 28, 2009 Page 1460 of 1650
REJ09B0313-0300
Module
Name
RCAN-
TL1
Register Name
Timer Compare Match Register 0_0 TCMR0_0
Timer Compare Match Register 1_0 TCMR1_0
Timer Compare Match Register 2_0 TCMR2_0
Tx-Trigger Time Selection
Register_0
Mailbox n Control 0_H_0
(n = 0 to 31)
Mailbox n Control 0_L_0
(n = 0 to 31)
Mailbox n Local Acceptance Filter
Mask 0_0 (n = 0 to 31)
Mailbox n Local Acceptance Filter
Mask 1_0 (n = 0 to 31)
Mailbox n Data 01_0 (n = 0 to 31)
Mailbox n Data 23_0 (n = 0 to 31)
Mailbox n Data 45_0 (n = 0 to 31)
Mailbox n Data 67_0 (n = 0 to 31)
Mailbox n Control 1_0 (n = 0 to 31)
Mailbox n Time Stamp_0
(n = 0 to 15, 30, 31)
Mailbox n Trigger Time_0
(n = 24 to 30)
Mailbox n TT Control_0
(n = 24 to 29)
Master Control Register_1
General Status Register_1
Bit Configuration Register 1_1
Bit Configuration Register 0_1
Interrupt Register_1
Interrupt Mask Register_1
Abbreviation
TTTSEL_0
MBn_CONTROL0_H_0
(n = 0 to 31)
MBn_CONTROL0_L_0
(n = 0 to 31)
MBn_LAFM0_0
(n = 0 to 31)
MBn_LAFM1_0
(n = 0 to 31)
MBn_DATA_01_0
(n = 0 to 31)
MBn_DATA_23_0
(n = 0 to 31)
MBn_DATA_45_0
(n = 0 to 31)
MBn_DATA_67_0
(n = 0 to 31)
MBn_CONTROL1_0
(n = 0 to 31)
MBn_TIMESTAMP_0
(n = 0 to 15, 30, 31)
MBn_TTT_0
(n = 24 to 30)
MBn_TTCONTROL_0
(n = 24 to 29)
MCR_1
GSR_1
BCR1_1
BCR0_1
IRR_1
IMR_1
Number
of Bits
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Address
H'FFFF0098
H'FFFF009C
H'FFFF00A0
H'FFFF00A4
H'FFFF0100
H'FFFF0102
H'FFFF0104
H'FFFF0106
H'FFFF0108
H'FFFF010A
H'FFFF010C
H'FFFF010E
H'FFFF0110
H'FFFF0112 +
n×32
H'FFFF0114
H'FFFF0116
H'FFFF0800
H'FFFF0802
H'FFFF0804
H'FFFF0806
H'FFFF080A
H'FFFF0808
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
+ n×32
Access
Size
16
16
16
16
16, 32
16
16, 32
16
8, 16, 32
8, 16
8, 16, 32
8, 16
8, 16
16
16
16
16
16
16
16
16
16