R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1568

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 Electrical Characteristics
31.4.2
Table 31.7 Control Signal Timing
Conditions: V
Rev. 3.00 Sep. 28, 2009 Page 1536 of 1650
REJ09B0313-0300
Item
RES pulse width Exit from standby mode
TRST pulse width
NMI pulse width
IRQ pulse width
PINT pulse width
IRQOUT/REFOUT output delay time
BREQ setup time
BREQ hold time
BACK delay time
Bus buffer off time 1
Bus buffer off time 2
Bus buffer on time 1
Bus buffer on time 2
BACK setup time when bus buffer off
Control Signal Timing
AV
V
USBAPV
CC
SS
CC
= PLLV
= PLLV
= 3.0 to 3.6 V, USBAV
or change the
multiplication ratio of the
PLL circuit
Other than above
Exit from standby mode t
Other than above
Exit from standby mode t
Other than above
SS
= 0 V, T
SS
CC
= PV
= USBDV
SS
a
= AV
= −20 to 85 °C
CC
SS
= 1.1 to 1.3 V, PV
= USBDV
CC
Symbol Min.
t
t
t
t
t
t
t
t
t
t
t
t
= 1.1 to 1.3 V, USBAPV
RESW
TRSW
NMIW
IRQW
PINTW
IRQOD
BREQS
BREQH
BACKD
BOFF1
BOFF2
BON1
BON2
BACKS
SS
= USBAV
10
20
20
10
20
10
20
20
—
1/2t
1/2t
—
—
—
—
—
0
Bφ = 66.66 MHz
cyc
cyc
CC
= USBDPV
+ 7 —
+ 2 —
SS
Max.
—
—
—
—
—
—
—
—
100
1/2t
15
15
15
15
—
= USBDPV
CC
cyc
= 3.0 to 3.6 V,
+ 13 ns
CC
= 3.0 to 3.6 V,
Unit
ms
t
t
ms
t
ms
t
t
ns
ns
ns
ns
ns
ns
ns
ns
SS
cyc
cyc
cyc
cyc
cyc
=
Figure
Figure 31.9
Figure 31.10
Figure 31.11
Figure 31.12