R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1596

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 31 Electrical Characteristics
Rev. 3.00 Sep. 28, 2009 Page 1564 of 1650
REJ09B0313-0300
A12/A11
D31 to D0
A25 to A0
TENDn *
Notes: 1. An address pin to be connected to pin A10 of SDRAM.
(Bank Active Mode: PRE + ACT + WRITE Commands, Different Row Addresses,
RASU/L
CASU/L
RD/WR
DQMxx
DACKn
Figure 31.35 Synchronous DRAM Burst Write Bus Cycle (Four Write Cycles)
CKIO
CKE
CSn
BS
*
1
2
2. The waveform for DACKn and TENDn is when active low is specified.
t
t
t
RASD1
t
DQMD1
t
t
RWD1
CSD1
t
AD1
AD1
DACD
Tp
t
WTRCD = 0 Cycle, TRWL = 0 Cycle)
t
RWD1
RASD1
t
AD1
Row address
Tpw
t
RASD1
Tr
t
t
t
RWD1
RASD1
t
t
WDD2
AD1
CASD1
t
t
AD1
BSD
Tc1
(High)
t
WDH2
t
AD1
Column address
Tc2
WRIT command
t
AD1
Tc3
t
t
WDD2
AD1
Tc4
t
t
t
DQMD1
t
t
DACD
t
CASD1
WDH2
BSD
t
t
t
RWD1
AD1
AD1
CSD1