R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1654

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 3.00 Sep. 28, 2009 Page 1622 of 1650
REJ09B0313-0300
Item
10.3.8 DMA Operation
Register (DMAOR)
Page
415
416
Revision (See Manual for Details)
Table amended
Bit
Notes added
Notes: 1. Only 0 can be written to clear the flag after 1 is
2
1
Bit Name
AE
NMIF
2. If the flag is read at the same timing it is set to 1,
read.
the read data will be 0, but the internal state may
be the same as reading 1. Therefore, if 0 is written
to the flag, the flag will be cleared to 0 because the
internal state is the same as when writing 0 after
reading 1.
For details, refer to section 10.5.5, Notes on Using
Flag Bits.
Initial
Value
0
0
R/W
R/(W)*
R/(W)*
1
1
Description
Address Error Flag
Indicates whether an address error has occurred by
the DMAC. When this bit is set, even if the DE bit in
CHCR and the DME bit in DMAOR are set to 1, DMA
transfer is not enabled. This bit can only be cleared by
writing 0 after reading 1.*
0: No DMAC address error
1: DMAC address error occurred
[Clearing condition]
•
NMI Flag
Indicates that an NMI interrupt occurred. When this bit
is set, even if the DE bit in CHCR and the DME bit in
DMAOR are set to 1, DMA transfer is not enabled. This
bit can only be cleared by writing 0 after reading 1.*
When the NMI is input, the DMA transfer in progress
can be done in one transfer unit. Even if the NMI
interrupt is input while the DMAC is not in operation,
the NMIF bit is set to 1.
0: No NMI interrupt
1: NMI interrupt occurred
[Clearing condition]
•
Writing 0 after reading AE = 1*
Writing 0 after reading NMIF = 1*
2
2
2
2