R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1658

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 3.00 Sep. 28, 2009 Page 1626 of 1650
REJ09B0313-0300
Item
15.3.8 Bit Rate Register
(SCBRR)
Table 15.5 Bit Rates
and SCBRR Settings
(Clock Synchronous
Mode)
15.5 SCIF Interrupts
16.4.5 SSU Mode
Figure 16.6 Flowchart
Example of Data
Transmission (SSU
Mode)
Figure 16.9 Flowchart
Example of Simultaneous
Transmission/Reception
(SSU Mode)
Page
750
785
816
821
Revision (See Manual for Details)
Table amended
Description amended
When the RIE bit is set to 0 and the REIE bit is set to 1, the
SCIF requests an ERI or BRI interrupt without requesting an
RXI interrupt.
Figure amended
Figure amended
Bit Rate
(bit/s)
250
500
1 k
2.5 k
5 k
10 k
25 k
50 k
100 k
250 k
500 k
1 M
2 M
n
3
2
2
1
1
0
0
0
0
0
0
0
0
[1]
[2]
[1]
[2]
8
124
249
124
199
99
199
79
39
19
7
3
1
0*
N
Write transmit data to SSTDR
Write transmit data to SSTDR
Read the TDRE bit in SSSR.
Read the TDRE bit in SSSR
TDRE automatically cleared
TDRE automatically cleared
n
3
3
2
2
1
1
0
0
0
0
0
0
0
Initial setting
Yes
16
Initial setting
TDRE = 1?
TDRE = 1?
Yes
N
249
124
249
99
199
99
159
79
39
15
7
3
1
Start
Start
n
3
3
2
2
1
1
0
0
—
—
—
—
Pφ (MHz)
28.7
N
223
111
178
89
178
71
143
71
—
—
—
—
No
n
3
3
2
2
1
1
0
0
0
0
—
—
No
30
233
116
187
93
187
74
149
74
29
14
—
—
N
3
3
2
2
1
1
0
0
0
—
—
—
n
33
255
128
205
102
205
82
164
82
32
—
—
—
N