R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1660

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Rev. 3.00 Sep. 28, 2009 Page 1628 of 1650
REJ09B0313-0300
Item
18.3 Register
Description
Table 18.2 Register
Description
18.3.1 Control Register
(SSICR)
18.5.1 Limitations from
Underflow or Overflow
during DMA Operation
19.7 CAN Bus Interface 1015
Page
879
885
912
Revision (See Manual for Details)
Table amended
Channel
Table amended
Title amended and description replaced
Description amended
A bus transceiver IC is necessary to connect this LSI to a
CAN bus. A Renesas HA13721 transceiver IC and its
compatible products are recommended. As the CRx and CTx
pins use 3 V, an external level shifter is necessary. Figure
19.27 shows a sample connection diagram.
Bit
0
1
2
3
3
Bit Name
MUEN
Register Name
Control register 0
Status register 0
Transmit data register 0
Receive data register 0
Control register 1
Status register 1
Transmit data register 1
Receive data register 1
Control register 2
Status register 2
Transmit data register 2
Receive data register 2
Control register 3
Status register 3
Transmit data register 3
Receive data register 3
Initial
Value
0
R/W
R/W
Abbrevia-
tion
SSICR_0
SSISR_0
SSITDR_0
SSIRDR_0
SSICR_1
SSISR_1
SSITDR_1
SSIRDR_1
SSICR_2
SSISR_2
SSITDR_2
SSIRDR_2
SSICR_3
SSISR_3
SSITDR_3
SSIRDR_3
Description
Mute Enable
0: Module is not muted.
1: Module is muted.
Note: When mute is enabled, the serial data to be output
is replaced with zeros, but data transfer within the
module does not stop. Therefore, dummy data
must be written to SSITRD to prevent a transmit
underflow from occurring.
R/W
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
R/W
R/W*
R/W
R
Initial Value
H'00000000
H'02000003
H'00000000
H'00000000
H'00000000
H'02000003
H'00000000
H'00000000
H'00000000
H'02000003
H'00000000
H'00000000
H'00000000
H'02000003
H'00000000
H'00000000
Address
H'FFFFC000
H'FFFFC004
H'FFFFC008
H'FFFFC00C
H'FFFFC800
H'FFFFC804
H'FFFFC808
H'FFFFC80C
H'FFFFD000
H'FFFFD004
H'FFFFD008
H'FFFFD00C
H'FFFFD800
H'FFFFD804
H'FFFFD808
H'FFFFD80C
Access
Size
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32