R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1663

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Item
24.3.6 LCDC Start
Address Register for
Lower Display Data Fetch
(LDSARL)
24.3.10 LCDC
Horizontal Character
Number Register
(LDHCNR)
24.4.1 LCD Module
Sizes which Can Be
Displayed in this LCDC
27.1 Features
Table 27.3 Number of
Cycles for Access to On-
Chip High-Speed RAM
from the ID Bus
Page
1247
1251
1269
1394
Revision (See Manual for Details)
Description amended
When a DSTN panel is used, LDSARL specifies the fetch
start address for the lower side of the panel. The register
setting is updated with the Vsync timing when the LCDC is
active.
Notes amended
Notes: 2. Set HDCN according to the display resolution as
Description deleted
This LSI has a maximum 32-burst memory read operation
and a 2.4-kbyte line buffer, so although a complete
breakdown of the display is unlikely, there may be some
problems with the display depending on the combination.
Description added
•
On-chip high-speed RAM: the number of cycles for access to
read or write from buses F and I is one cycle of Iφ. Number of
cycles for access from the ID bus depend on the ratio of the
internal clock (Iφ) to the bus clock (Bφ). Table 31.3 indicates
number of cycles for access from the ID bus.
Table added
Description added
On-chip data retention RAM: The number of cycles required
to read or write from the IC bus or ID bus ranges from 1 Bφ +
2 Pφ (minimum) to 3 Pφ (maximum).
Number of access cycles
follows:
1 bpp: (multiple number of 16) − 1 [1 line is
multiple number of 128 pixel]
2 bpp: (multiple number of 8) − 1 [1 line is multiple
number of 64 pixel]
4 bpp: (multiple number of 4) − 1 [1 line is multiple
number of 32 pixel]
6 bpp/8 bpp: (multiple number of 2) − 1 [1 line is
multiple number of 16 pixel]
Rev. 3.00 Sep. 28, 2009 Page 1631 of 1650
REJ09B0313-0300