R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1675

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

DMAC timing....................................... 1575
DREQ pin sampling timing .................... 440
DTCH interrupt..................................... 1189
Dual address mode.................................. 432
E
ECC code.............................................. 1092
ECC error check ................................... 1092
Effective address calculation .................... 58
Electrical characteristics ....................... 1521
Endian..................................................... 297
Equation for getting SCBRR value......... 744
Example of time triggered system ........ 1005
Exception handling ................................. 123
Exception handling state........................... 91
Exception handling vector table ............. 127
Exception source generation
immediately after delayed branch
instruction ............................................... 143
Exceptions triggered by instructions....... 139
External request mode ............................ 423
External trigger input timing................. 1038
F
Fixed mode ............................................. 428
FLCTL interrupt requests ..................... 1095
FLCTL timing....................................... 1588
Floating point operation instructions ...... 142
Floating-point exceptions ....................... 103
Floating-point format................................ 94
Floating-point operation instructions........ 85
Floating-point ranges ................................ 96
Floating-point registers............................. 99
Floating-point unit (FPU) ......................... 93
Flow of the user break operation ............ 210
Format of double-precision
floating-point number ............................... 94
Format of single-precision
foating-point number ................................ 94
FPU exception handling ......................... 103
FPU exception sources............................ 103
FPU-related CPU instructions................... 87
Frame update interrupt.......................... 1187
Full-scale error ...................................... 1040
G
General illegal instructions ..................... 141
General registers ....................................... 47
Global base register (GBR)....................... 49
H
Halt mode................................................ 991
H-UDI commands................................. 1440
H-UDI interrupt ............................ 165, 1443
H-UDI reset........................................... 1443
H-UDI timing........................................ 1601
I
I/O port timing ...................................... 1600
I/O ports ................................................ 1365
I
I
ID reorder................................................ 939
IIC3 timing............................................ 1582
Immediate data.......................................... 56
Immediate data accessing.......................... 56
Immediate data format .............................. 53
Influences on absolute precision ........... 1044
Initial values of control registers............... 51
Initial values of general registers .............. 51
Initial values of system registers ............... 51
Instruction features.................................... 54
Instruction format...................................... 63
Instruction set............................................ 67
Integer division instructions.................... 141
Internal arbitration for transmission........ 995
Interrupt controller (INTC) ..................... 149
Interrupt exception handling ................... 138
Interrupt exception handling vectors
and priorities ........................................... 169
2
2
C bus format ......................................... 852
C bus interface 3 (IIC3) ........................ 833
Rev. 3.00 Sep. 28, 2009 Page 1643 of 1650
REJ09B0313-0300