R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 1676

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Interrupt priority level ............................ 137
Interrupt response time ........................... 182
Interrupt transfers ................................. 1218
IRQ interrupts......................................... 165
Isochronous transfers............................ 1219
J
Jump table base register (TBR) ................ 49
L
LCD controller (LCDC) ....................... 1233
LCD module power-supply states ........ 1285
LCDC timing ........................................ 1598
Load-store architecture ............................. 54
Local acceptance filter mask (LAFM).... 930
Logic operation instructions ..................... 80
Low-frequency mode.............................. 352
Low-power SDRAM .............................. 357
LRU ........................................................ 221
M
Mailbox........................................... 917, 921
Mailbox configuration ............................ 929
Mailbox control ...................................... 917
Manual reset ........................................... 132
Master receive operation......................... 855
Master transmit operation ....................... 853
Memory-mapped cache .......................... 234
Message control field.............................. 926
Message data fields................................. 931
Message receive sequence .................... 1009
Message transmission request....... 995, 1004
Micro processor interface (MPI) ............ 917
Module standby function ...................... 1434
Module standby mode setting................. 831
MPX-I/O interface.................................. 312
MTU2 functions ..................................... 450
MTU2 interrupts..................................... 599
MTU2 output pin initialization............... 630
MTU2 timing........................................ 1576
Rev. 3.00 Sep. 28, 2009 Page 1644 of 1650
REJ09B0313-0300
Multi mode............................................ 1031
Multi-function timer pulse unit 2
(MTU2)................................................... 449
Multiplexed pins (port A) ..................... 1301
Multiplexed pins (port B)...................... 1301
Multiplexed pins (port C)...................... 1302
Multiplexed pins (port D) ..................... 1303
Multiplexed pins (port E)...................... 1304
Multiplexed pins (port F) ...................... 1306
Multiply and accumulate register high
(MACH).................................................... 50
Multiply and accumulate register low
(MACL) .................................................... 50
Multiply/Multiply-and-accumulate
operations.................................................. 55
N
NMI interrupt.......................................... 165
Noise filter .............................................. 865
Non-compressed modes .......................... 893
Nonlinearity error ................................. 1040
Non-numbers (NaN) ................................. 97
Normal space interface ........................... 304
Note on using a PLL oscillation circuit... 121
Notes on display-off mode
(LCDC stopped).................................... 1286
NRDY interrupt .................................... 1181
NYET handshake responses ................. 1217
O
Offset error............................................ 1040
On-chip peripheral module interrupts ..... 167
On-chip peripheral module request......... 425
Operation for hardware rotation............ 1286
Operation in asynchronous mode............ 766
Operation in clocked synchronous mode 777
Output load circuit ................................ 1603
P
Package dimensions.................... 1613, 1615