R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 23

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

17.5 Interrupt Requests .............................................................................................................. 870
17.6 Bit Synchronous Circuit..................................................................................................... 871
17.7 Usage Notes ....................................................................................................................... 873
Section 18 Serial Sound Interface (SSI) ............................................................875
18.1 Features.............................................................................................................................. 875
18.2 Input/Output Pins ............................................................................................................... 878
18.3 Register Description........................................................................................................... 879
18.4 Operation Description ........................................................................................................ 892
18.5 Usage Notes ....................................................................................................................... 912
Section 19 Controller Area Network (RCAN-TL1) ..........................................913
19.1 Summary............................................................................................................................ 913
17.4.1 I
17.4.2 Master Transmit Operation ................................................................................... 853
17.4.3 Master Receive Operation..................................................................................... 855
17.4.4 Slave Transmit Operation ..................................................................................... 857
17.4.5 Slave Receive Operation....................................................................................... 860
17.4.6 Clocked Synchronous Serial Format..................................................................... 861
17.4.7 Noise Filter ........................................................................................................... 865
17.4.8 Example of Use..................................................................................................... 866
17.7.1 Note on the Setting of ICCR1.CKS[3:0]............................................................... 873
17.7.2 Settings for Multi-Master Operation..................................................................... 873
17.7.3 Note on Master Receive Mode.............................................................................. 873
17.7.4 Note on Setting ACKBT in Master Receive Mode............................................... 874
17.7.5 Note on the States of Bits MST and TRN when Arbitration Is Lost..................... 874
18.3.1 Control Register (SSICR) ..................................................................................... 880
18.3.2 Status Register (SSISR) ........................................................................................ 886
18.3.3 Transmit Data Register (SSITDR) ........................................................................ 891
18.3.4 Receive Data Register (SSIRDR) ......................................................................... 891
18.4.1 Bus Format............................................................................................................ 892
18.4.2 Non-Compressed Modes....................................................................................... 893
18.4.3 Operation Modes................................................................................................... 903
18.4.4 Transmit Operation ............................................................................................... 904
18.4.5 Receive Operation................................................................................................. 907
18.4.6 Temporary Stop and Restart Procedures in Transmit Mode ................................. 910
18.4.7 Serial Bit Clock Control........................................................................................ 911
18.5.1 Limitations from Underflow or Overflow during DMA Operation ...................... 912
19.1.1 Overview............................................................................................................... 913
19.1.2 Scope..................................................................................................................... 913
2
C Bus Format...................................................................................................... 852
Rev. 3.00 Sep. 28, 2009 Page xxi of xxx
REJ09B0313-0300