R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 245

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

7.4.4
When a user break interrupt request is received, the address of the instruction from where
execution is to be resumed is saved to the stack, and the exception handling state is entered. If the
C bus (FAB)/instruction fetch cycle is specified as a break condition, the instruction at which the
break should occur can be uniquely determined. If the C bus/data access cycle or I bus/data access
cycle is specified as a break condition, the instruction at which the break should occur cannot be
uniquely determined.
1. When C bus (FAB)/instruction fetch (before instruction execution) is specified as a break
2. When C bus (FAB)/instruction fetch (after instruction execution) is specified as a break
3. When C bus/data access cycle or I bus/data access cycle is specified as a break condition:
condition:
The address of the instruction that matched the break condition is saved to the stack. The
instruction that matched the condition is not executed, and the break occurs before it. However
when a delay slot instruction matches the condition, the instruction is executed, and the branch
destination address is saved to the stack.
condition:
The address of the instruction following the instruction that matched the break condition is
saved to the stack. The instruction that matches the condition is executed, and the break occurs
before the next instruction is executed. However when a delayed branch instruction or delay
slot matches the condition, the instruction is executed, and the branch destination address is
saved to the stack.
The address after executing several instructions of the instruction that matched the break
condition is saved to the stack.
Value of Saved Program Counter
Rev. 3.00 Sep. 28, 2009 Page 213 of 1650
Section 7 User Break Controller (UBC)
REJ09B0313-0300