R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 292

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Bus State Controller (BSC)
• CS2WCR, CS3WCR
Initial value:
Initial value:
Rev. 3.00 Sep. 28, 2009 Page 260 of 1650
REJ09B0313-0300
Bit
31 to 21 ⎯
20
19 to 11 ⎯
R/W:
R/W:
Bit:
Bit:
BAS
Bit Name
31
15
R
R
0
0
-
-
30
14
R
R
0
0
-
-
29
13
R
R
0
0
-
-
Initial
Value
All 0
0
All 0
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
R/W
R
R/W
R
R/W
26
10
R
0
1
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
SRAM with Byte Selection Byte Access Select
Specifies the WEn and RD/WR signal timing when the
SRAM interface with byte selection is used.
0: Asserts the WEn signal at the read timing and
1: Asserts the WEn signal during the read access cycle
Reserved
These bits are always read as 0. The write value
should always be 0.
R/W
25
R
0
9
0
-
WR[3:0]
asserts the RD/WR signal during the write access
cycle.
and asserts the RD/WR signal at the write timing.
R/W
24
R
0
8
1
-
R/W
23
R
0
7
0
-
R/W
WM
22
R
0
6
0
-
21
R
R
0
5
0
-
-
R/W
BAS
20
R
0
4
0
-
19
R
R
0
3
0
-
-
18
R
R
0
2
0
-
-
17
R
R
0
1
0
-
-
16
R
R
0
0
0
-
-