R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 321

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

9.4.4
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Initial value:
Initial value:
Bit
31 to 21 ⎯
20, 19
18
17, 16
R/W:
R/W:
Bit:
Bit:
SDRAM Control Register (SDCR)
Bit Name
A2ROW[1:0] 00
⎯
A2COL[1:0]
31
15
R
R
0
0
-
-
30
14
R
R
0
0
-
-
DEEP SLOW RFSH RMODEPDOWN BACTV
R/W
29
13
R
0
0
-
Initial
Value
All 0
0
00
R/W
28
12
R
0
0
-
R/W
27
11
R
0
0
-
R/W
R
R/W
R
R/W
R/W
26
10
R
0
0
-
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Number of Bits of Row Address for Area 2
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
Reserved
This bit is always read as 0. The write value should
always be 0.
Number of Bits of Column Address for Area 2
Specify the number of bits of column address for
area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
R/W
25
R
0
9
0
-
R/W
24
R
0
8
0
-
23
R
R
0
7
0
-
-
Rev. 3.00 Sep. 28, 2009 Page 289 of 1650
22
R
R
0
6
0
-
-
Section 9 Bus State Controller (BSC)
21
R
R
0
5
0
-
-
R/W
R/W
A2ROW[1:0]
A3ROW[1:0]
20
0
4
0
R/W
R/W
19
0
3
0
REJ09B0313-0300
18
R
R
0
2
0
-
-
R/W
R/W
A2COL[1:0]
A3COL[1:0]
17
0
1
0
R/W
R/W
16
0
0
0