R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 372

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 9 Bus State Controller (BSC)
(7)
Bank Active
The SDRAM bank function can be used to support high-speed access to the same row address.
When the BACTV bit in SDCR is 1, access is performed using commands without auto-precharge
(READ or WRIT). This function is called bank-active function. This function is valid only for
either the upper or lower bits of area 3. When area 3 is set to bank-active mode, area 2 should be
set to normal space or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM or
both the upper and lower bits of area 3 are connected to SDRAM, auto precharge mode must be
set.
When the bank-active function is used, precharging is not performed when the access ends. When
accessing the same row address in the same bank, it is possible to issue the READ or WRIT
command immediately, without issuing an ACTV command. As SDRAM is internally divided
into several banks, it is possible to activate one row address in each bank. If the next access is to a
different row address, a PRE command is first issued to precharge the relevant bank, then when
precharging is completed, the access is performed by issuing an ACTV command followed by a
READ or WRIT command. If this is followed by an access to a different row address, the access
time will be longer because of the precharging performed after the access request is issued. The
number of cycles between issuance of the PRE command and the ACTV command is determined
by the WTRP1 and WTPR0 bits in CS3WCR.
In a write, when an auto-precharge is performed, a command cannot be issued to the same bank
for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode
is used, READ or WRIT commands can be issued successively if the row address is the same. The
number of cycles can thus be reduced by Trwl + Tap cycles for each write.
There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of tRAS.
A burst read cycle without auto-precharge is shown in figure 9.22, a burst read cycle for the same
row address in figure 9.23, and a burst read cycle for different row addresses in figure 9.24.
Similarly, a burst write cycle without auto-precharge is shown in figure 9.25, a burst write cycle
for the same row address in figure 9.26, and a burst write cycle for different row addresses in
figure 9.27.
In figure 9.23, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that
issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for
the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS
Rev. 3.00 Sep. 28, 2009 Page 340 of 1650
REJ09B0313-0300