R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 373

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of
latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
When bank active mode is set, if only access cycles to the respective banks in the area 3 space are
considered, as long as access cycles to the same row address continue, the operation starts with the
cycle in figure 9.22 or 9.25, followed by repetition of the cycle in figure 9.23 or 9.26. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, the bus cycle in figure 9.24 or 9.27 is executed instead of that in figure 9.23 or
9.26. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is
released as the result of bus arbitration.
Figure 9.22 Burst Read Timing (Bank Active, Different Bank, CAS Latency 1)
RASL, RASU
CASL, CASU
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
A12/A11*
D31 to D0
A25 to A0
DACKn*
RD/WR
DQMxx
CKIO
2. The waveform for DACKn is when active low is specified.
CS3
BS
1
2
Tr
Tc1
Td1
Tc2
Td2
Tc3
Rev. 3.00 Sep. 28, 2009 Page 341 of 1650
Td3
Tc4
Section 9 Bus State Controller (BSC)
Td4
Tde
REJ09B0313-0300