R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 415

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

In the above conditions, a total of four conditions, that is, condition [1] or [2] (either one is
effective), condition [3] or [4] (either one is effective), a set of conditions [5] to [7] (these are
generated successively, and therefore the sum of them should be taken as one set of idle cycles),
and condition [8] are generated at the same time. The maximum number of idle cycles among
these four conditions become the number of idle cycles on the external bus. To ensure the
minimum idle cycles, be sure to make register settings for condition [1] or [2].
Note:
Previous access
CKIO
CSn
A total of four conditions (condition [1] or [2], condition [3] or [4], a set of conditions [5] to [7],
and condition [8]) generate idle cycle at the same time. Accordingly, the maximum number of
cycles among these four conditions become the number of idle cycles.
[1] DMAIW[2:0] setting in CMNCR
[2] IWW[2:0] setting in CSnBCR
[3] WTRP[1:0] setting in CSnWCR
[4] WM setting in CSnWCR
[5] Read
Idle cycle after access
IWRWD[2:0] setting in CSnBCR
IWRWS[2:0] setting in CSnBCR
IWRRD[2:0] setting in CSnBCR
IWRRS[2:0] setting in CSnBCR
TRWL[1:0] setting in CSnWCR
WTRC[1:0] setting in CSnWCR
data
transfer
Figure 9.53 Idle Cycle Conditions
[6] Internal bus idle cycles, etc.
External bus idle cycles
Idle cycle before access
Either one of them
is effective
Either one of them
is effective
[8] Idle cycles
Rev. 3.00 Sep. 28, 2009 Page 383 of 1650
between
different
memory types
[7] Write
Section 9 Bus State Controller (BSC)
data
wait
Condition [1] or [2]
Condition [3] or [4]
Set of conditions
[5] to [7]
Condition [8]
Next access
REJ09B0313-0300