R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 427

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Figure 10.1 shows the block diagram of the DMAC.
RDMATCR:
DMATCR:
RSAR:
SAR:
RDAR:
DAR:
[Legend]
(with acknowledge)
DREQ0 to DREQ3
DACK0 to DACK3,
TEND0, TEND1
(memory mapped)
External ROM
External RAM
External device
External device
peripheral module
DMA transfer acknowledge signal
memory
On-chip
Interrupt controller
On-chip
DMA transfer request signal
DMA reload transfer count register
DMA transfer count register
DMA reload source address register
DMA source address register
DMA reload destination address register
DMA destination address register
Figure 10.1 Block Diagram of DMAC
Bus state
controller
CHCR:
DMAOR:
DMARS0 to DMARS3:
HEIn:
DEIn:
n = 0 to 7
HEIn
DEIn
interface
Register
Request
Iteration
Start-up
Section 10 Direct Memory Access Controller (DMAC)
control
priority
control
control
Bus
control
DMA channel control register
DMA operation register
DMA extension resource selectors 0 to 3
DMA transfer half-end interrupt request to the CPU
DMA transfer end interrupt request to the CPU
Rev. 3.00 Sep. 28, 2009 Page 395 of 1650
DMAC module
RDMATCRn
to DMARS3
DMATCRn
DMARS0
DMAOR
RDARn
CHCRn
RSARn
SARn
DARn
REJ09B0313-0300

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