R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 462

IC SUPERH MPU ROMLESS 240QFP

R5S72030W200FP

Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Datasheets

Specifications of R5S72030W200FP

Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-

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Section 10 Direct Memory Access Controller (DMAC)
Figure 10.4 shows how the priority order changes when channel 0 and channel 3 transfers are
requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The
DMAC operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
4. When the channel 0 transfer ends, channel 0 is given the lowest priority among the round-robin
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
6. When the channel 1 transfer ends, channel 1 is given the lowest priority among the round-robin
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 are lowered in priority so that channel 3 is
Rev. 3.00 Sep. 28, 2009 Page 430 of 1650
REJ09B0313-0300
transfer).
waiting)
channels.
(channel 3 waits for transfer).
channels.
given the lowest priority among the round-robin channels.
Transfer request
(1) Channels 0 and 3
(3) Channel 1
Figure 10.4 Changes in Channel Priority in Round-Robin Mode
Waiting channel(s)
1, 3
3
3
None
(2) Channel 0 transfer start
(4) Channel 0 transfer ends
(5) Channel 1 transfer starts
(6) Channel 1 transfer ends
(7) Channel 3 transfer starts
(8) Channel 3 transfer ends
DMAC operation
Priority order
changes
Priority order
changes
Priority order
changes
Channel priority
0 > 1 > 2 > 3 > 4 > 5 > 6 > 7
1 > 2 > 3 > 0 > 4 > 5 > 6 > 7
2 > 3 > 0 > 1 > 4 > 5 > 6 > 7
0 > 1 > 2 > 3 > 4 > 5 > 6 > 7

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