R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 477

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

10.5.3
In case that one or more channels are set that transfer request source is external request signal
DREQ, please use one of the following four ways.
1) Please set all channels to cycle-steal mode.
2) Please set all channels to burst-mode with all of the following three conditions.
3) If there are both of one or more channels set to cycle-steal mode and one or more channels set
4) Please use only one channel.
If using other than the above four ways, there is a possibility that DACKn pin and TENDn pin
show wrong transfer channel and since then until power-on reset DMA transfer is unavailable.
Additionally if this state occurs in burst-mode, CPU becomes unable to fetch instructions, then
system becomes suspended.
2-1) Please set channel priority mode to fixed mode 1 or fixed mode 2.
2-2) Please set all channels to dual-address mode.
2-3) Please set transfer source address and transfer destination address of each channels to one
to burst mode, please use with all of the following three conditions.
3-1) Please set channel priority mode to fixed mode 1 or fixed mode 2.
3-2) Please set all channels to dual-address mode.
3-3) Please set transfer source address and transfer destination address of each channels to one
A. transfer source address:
B. transfer source address:
C. transfer source address:
A. transfer source address:
B. transfer source address:
C. transfer source address:
of the followings.
of the followings.
Notice about using external request mode
transfer destination address: external address space
transfer destination address: internal address space
transfer destination address: internal address space
transfer destination address: external address space
transfer destination address: internal address space
transfer destination address: internal address space
external address space
external address space
internal address space
external address space
external address space
internal address space
Section 10 Direct Memory Access Controller (DMAC)
Rev. 3.00 Sep. 28, 2009 Page 445 of 1650
REJ09B0313-0300