R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 498

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.3
The TIOR registers are 8-bit readable/writable registers that control the TGR registers. The MTU2
has a total of eight TIOR registers, two each for channels 0, 3, and 4, one each for channels 1 and
2.
TIOR should be set while TMDR is set in normal operation, PWM mode, or phase counting mode.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
• TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIORH_4
Rev. 3.00 Sep. 28, 2009 Page 466 of 1650
REJ09B0313-0300
Bit
7 to 4
3 to 0
Bit Name
IOB[3:0]
IOA[3:0]
Timer I/O Control Register (TIOR)
Initial value:
Initial
Value
0000
0000
R/W:
Bit:
R/W
7
0
R/W
R/W
R/W
R/W
6
0
IOB[3:0]
Description
I/O Control B0 to B3
Specify the function of TGRB.
See the following tables.
TIORH_0: Table 11.11
TIOR_1:
TIOR_2:
TIORH_3: Table 11.15
TIORH_4: Table 11.17
I/O Control A0 to A3
Specify the function of TGRA.
See the following tables.
TIORH_0: Table 11.19
TIOR_1:
TIOR_2:
TIORH_3: Table 11.23
TIORH_4: Table 11.25
R/W
5
0
R/W
4
0
Table 11.13
Table 11.14
Table 11.21
Table 11.22
R/W
3
0
R/W
2
0
IOA[3:0]
R/W
1
0
R/W
0
0