R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 626

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.4.9
A/D converter start requests can be issued in channel 4 by making settings in the timer A/D
converter start request control register (TADCR), timer A/D converter start request cycle set
registers (TADCORA_4 and TADCORB_4), and timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4).
The A/D converter start request delaying function compares TCNT_4 with TADCORA_4 or
TADCORB_4, and when their values match, the function issues a respective A/D converter start
request (TRG4AN or TRG4BN).
A/D converter start requests (TRG4AN and TRG4BN) can be skipped in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
TADCR.
• Example of Procedure for Specifying A/D Converter Start Request Delaying Function
Rev. 3.00 Sep. 28, 2009 Page 594 of 1650
REJ09B0313-0300
Figure 11.73 shows an example of procedure for specifying the A/D converter start request
delaying function.
Set A/D converter start request cycle
• Set the timing of transfer
• Set linkage with interrupt skipping
• Enable A/D converter start
from cycle set buffer register
request delaying function
A/D Converter Start Request Delaying Function
A/D converter start request
A/D converter start request
Figure 11.73 Example of Procedure for Specifying A/D Converter
delaying function
delaying function
Start Request Delaying Function
[1]
[2]
[1] Set the cycle in the timer A/D converter start request cycle
[2] Use bits BF1 and BF2 in the timer A/D converter start
Notes: 1. Perform TADCR setting while TCNT_4 is stopped.
• Specify whether to link with interrupt skipping through bits
• Use bits TU4AE, DT4AE, UT4BE, and DT4BE to enable
buffer register (TADCOBRA_4 or TADCOBRB_4) and timer
A/D converter start request cycle register (TADCORA_4 or
TADCORB_4). (The same initial value must be specified in
the cycle buffer register and cycle register.)
request control register (TADCR) to specify the timing of
transfer from the timer A/D converter start request cycle
buffer register to A/D converter start request cycle register.
ITA3AE, ITA4VE, ITB3AE, and ITB4VE.
A/D conversion start requests (TRG4AN or TRG4BN).
2. Do not set BF1 to 1 when complementary PWM mode
3. Do not set ITA3AE, ITA4VE, ITB3AE, ITB4VE,
is not selected.
DT4AE, or DT4BE to 1 when complementary PWM
mode is not selected.