R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 651

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

11.7.8
When the buffer transfer timing is set at the TCNT clear by the buffer transfer mode register
(TBTM), if TCNT clear occurs in the T2 state of a TGR write cycle, the data that is transferred to
TGR by the buffer operation is the data before write.
Figure 11.103 shows the timing in this case.
Figure 11.103 Contention between Buffer Register Write and TCNT Clear
Address
Write signal
TCNT clear
signal
Buffer transfer
signal
Buffer register
TGR
Contention between Buffer Register Write and TCNT Clear
Pφ
N
TGR write cycle
Buffer register
T1
address
Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
T2
Rev. 3.00 Sep. 28, 2009 Page 619 of 1650
M
N
Buffer register write data
REJ09B0313-0300