R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 695

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

This LSI has an on-chip compare match timer (CMT) consisting of a two-channel 16-bit timer.
The CMT has a16-bit counter, and can generate interrupts at set intervals.
12.1
• Independent selection of four counter input clocks at two channels
• Selection of DMA transfer request or interrupt request generation on compare match by
• When not in use, the CMT can be stopped by halting its clock supply to reduce power
Figure 12.1 shows a block diagram of CMT.
[Legend]
CMSTR:
CMCSR:
CMCOR:
CMCNT:
CMI:
Any of four internal clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) can be selected.
DMAC setting
consumption.
Compare match timer start register
Compare match timer control/status register
Compare match constant register
Compare match counter
Compare match interrupt
Features
Control circuit
Section 12 Compare Match Timer (CMT)
CMI0
Pφ/8
Figure 12.1 Block Diagram of CMT
Pφ/32
Clock selection
Channel 0
Pφ/128
CMT
Module bus
Pφ/512
Control circuit
CMI1
Rev. 3.00 Sep. 28, 2009 Page 663 of 1650
Section 12 Compare Match Timer (CMT)
Pφ/8
Pφ/32
Clock selection
Channel 1
Pφ/128
Peripheral bus
REJ09B0313-0300
Pφ/512
interface
Bus