R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 701

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

12.3
12.3.1
When an internal clock is selected with the CKS[1:0] bits in CMCSR and the STR bit in CMSTR
is set to 1, CMCNT starts incrementing using the selected clock. When the values in CMCNT and
CMCOR match, CMCNT is cleared to H'0000 and the CMF flag in CMCSR is set to 1. When the
CMIE bit in CMCSR is set to 1 at this time, a compare match interrupt (CMI) is requested.
CMCNT then starts counting up again from H'0000.
Figure 12.2 shows the operation of the compare match counter.
12.3.2
One of four clocks (Pφ/8, Pφ/32, Pφ/128, and Pφ/512) obtained by dividing the peripheral clock
(Pφ) can be selected with the CKS1 and CKS0 bits in CMCSR. Figure 12.3 shows the timing.
Peripheral clock
Internal clock
Count clock
CMCNT
Operation
Interval Count Operation
CMCNT Count Timing
(Pφ)
CMCOR
H'0000
CMCNT value
Clock
N
Figure 12.2 Counter Operation
Figure 12.3 Count Timing
N
Counter cleared by compare
match with CMCOR
Rev. 3.00 Sep. 28, 2009 Page 669 of 1650
Section 12 Compare Match Timer (CMT)
Clock
N + 1
Time
REJ09B0313-0300
N + 1