R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 702

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 12 Compare Match Timer (CMT)
12.4
12.4.1
The CMT has channels and each of them to which a different vector address is allocated has a
compare match interrupt. When both the compare match flag (CMF) and the interrupt enable bit
(CMIE) are set to 1, the corresponding interrupt request is output. When the interrupt is used to
activate a CPU interrupt, the priority of channels can be changed by the interrupt controller
settings. For details, see section 6, Interrupt Controller (INTC).
Clear the CMF bit to 0 by the user exception handling routine. If this operation is not carried out,
another interrupt will be generated. The direct memory access controller (DMAC) can be set to be
activated when a compare match interrupt is requested. In this case, an interrupt is not issued to
the CPU. If the setting to activate the DMAC has not been made, an interrupt request is sent to the
CPU. The CMF bit is automatically cleared to 0 when data is transferred by the DMAC.
12.4.2
When CMCOR and CMCNT match, a compare match signal is generated at the last state in which
the values match (the timing when the CMCNT value is updated to H'0000) and the CMF bit in
CMCSR is set to 1. That is, after a match between CMCOR and CMCNT, the compare match
signal is not generated until the next CMCNT counter clock input. Figure 12.4 shows the timing of
CMF bit setting.
Rev. 3.00 Sep. 28, 2009 Page 670 of 1650
REJ09B0313-0300
Interrupts
Interrupt Sources and DMA Transfer Requests
Timing of Compare Match Flag Setting