R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 801

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Figure 15.3 shows a sample flowchart for initializing the SCIF.
After reading flags ER, DR, and BRK in SCFSR,
(leaving bits TIE, RIE, TE, and RE cleared to 0)
Set the RTRG1, RTRG0, TTRG1, TTRG0, and
and each flag in SCLSR, write 0 to clear them
Set the TFRST and RFRST bits in SCFCR to 1
Set the BGDM and ABCS bits in SCEMR
Set the CKE1 and CKE0 bits in SCSCR
Clear the TE and RE bits in SCSCR to 0
Set the TE and RE bits in SCSCR to 1,
Set data transfer format in SCSMR
and set the TIE, RIE, and REIE bits
clear TFRST and RFRST bits to 0
PFC setting for external pins used
MCE bits in SCFCR, and
Figure 15.3 Sample Flowchart for SCIF Initialization
Set value in SCBRR
Start of initialization
End of initialization
SCK, TxD, RxD
Section 15 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
[1]
[2]
[3]
[4]
[5]
Set the clock selection in SCSCR.
Be sure to clear bits TIE, RIE, TE,
and RE to 0.
Set the data transfer format in
SCSMR.
Write a value corresponding to the
bit rate into SCBRR. (Not
necessary if an external clock is
used.)
Sets PFC for external pins used.
Set as RxD input at receiving and
TxD at transmission.
However, no setting for SCK pin is
required when CKE[1:0] is 00.
In the case when internal synchronous
clock output is set, the SCK pin starts
outputting the clock at this stage.
Set the TE bit or RE bit in SCSCR
to 1. Also set the RIE, REIE, and
TIE bits. Setting the TE and RE bits
enables the TxD and RxD pins to be
used.
When transmitting, the SCIF will go
to the mark state; when receiving,
it will go to the idle state, waiting for
a start bit.
Rev. 3.00 Sep. 28, 2009 Page 769 of 1650
REJ09B0313-0300