R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 803
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
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In serial transmission, the SCIF operates as described below.
1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is
data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that
the TDFE flag in the serial status register (SCFSR) is set to 1 before writing transmit data to
SCFTDR. The number of data bytes that can be written is (16 – transmit trigger setting).
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the
FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register
(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt (TXI) request is
generated.
The serial transmit data is sent from the TxD pin in the following order.
A. Start bit: One-bit 0 is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is
D. Stop bit(s): One or two 1 bits (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial
transmission of the next frame is started.
not output can also be selected.)
sent.
Section 15 Serial Communication Interface with FIFO (SCIF)
Rev. 3.00 Sep. 28, 2009 Page 771 of 1650
REJ09B0313-0300
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