R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 809

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

15.4.3
In clock synchronous mode, the SCIF transmits and receives data in synchronization with clock
pulses. This mode is suitable for high-speed serial communication.
The SCIF transmitter and receiver are independent, so full-duplex communication is possible
while sharing the same clock. The transmitter and receiver are also 16-byte FIFO buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting or
receiving is in progress.
Figure 15.11 shows the general format in clock synchronous serial communication.
Serial clock
Serial data
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock.
In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB
(last). After output of the MSB, the communication line remains in the state of the MSB.
In clock synchronous mode, the SCIF receives data by synchronizing with the rising edge of the
serial clock.
Note: * High except in continuous transfer
Operation in Clock Synchronous Mode
Don't care
*
Figure 15.11 Data Format in Clock Synchronous Communication
LSB
Bit 0
Bit 1
One unit of transfer data (character or frame)
Bit 2
Section 15 Serial Communication Interface with FIFO (SCIF)
Bit 3
Bit 4
Rev. 3.00 Sep. 28, 2009 Page 777 of 1650
Bit 5
Bit 6
REJ09B0313-0300
MSB
Bit 7
Don't care
*