R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 811
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Figure 15.12 shows a sample flowchart for initializing the SCIF.
PFC setting for external pins used
Set RTRG[1:0] and TTRG[1:0] bits
Set TE and RE bits in SCSCR
Set TFRST and RFRST bits
in SCFCR, and clear TFRST
Figure 15.12 Sample Flowchart for SCIF Initialization
and BRK flags in SCFSR,
and RE bits cleared to 0)
Set data transfer format
Set CKE[1:0] in SCSCR
in SCFCR to 1 to clear
to 1, and set TIE, RIE,
After reading ER, DR,
Clear TE and RE bits
(leaving TIE, RIE, TE,
write 0 to clear them
Set value in SCBRR
Start of initialization
and RFRST bits to 0
End of initialization
the FIFO buffer
SCK, TxD, RxD
in SCSCR to 0
and REIE bits
in SCSMR
Section 15 Serial Communication Interface with FIFO (SCIF)
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Leave the TE and RE bits cleared
to 0 until the initialization almost
ends. Be sure to clear the TIE,
RIE, TE, and RE bits to 0.
Set the data transfer format in
SCSMR.
Set CKE[1:0].
Write a value corresponding to
the bit rate into SCBRR. This
is not necessary if an external
clock is used.
Sets PFC for external pins used.
Set as RxD input at receiving and
TxD at transmission.
Set the TE or RE bit in SCSCR
to 1. Also set the TIE, RIE, and
REIE bits to enable the TxD,
RxD, and SCK pins to be used.
When transmitting, the TxD pin
will go to the mark state.
When receiving in clocked
synchronous mode with the
synchronization clock output (clock
master) selected, a clock starts to
be output from the SCK pin at this
point.
Rev. 3.00 Sep. 28, 2009 Page 779 of 1650
REJ09B0313-0300
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