R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 833

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

16.3.5
SSSR is a status flag register for interrupts.
Bit
7
6
5, 4
Bit Name
⎯
ORER
⎯
SS Status Register (SSSR)
Initial value:
Initial
Value
0
0
All 0
R/W:
Bit:
R/W
R
R/W
R
R
7
0
-
ORER
R/W
6
0
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
Overrun Error
If the next data is received while RDRF = 1, an overrun
error occurs, indicating abnormal termination. SSRDR
stores 1-frame receive data before an overrun error
occurs and loses data to be received later. While ORER
= 1, consecutive serial reception cannot be continued.
Serial transmission cannot be continued, either. Note
that this bit has no effect during slave data receive
operation (MSS in SSCRH cleared to 0 and TE and RE
in SSER set to 0 and 1, respectively) in SSU mode
(SSUMS in SSCRL cleared to 0).
[Setting condition]
•
[Clearing condition]
•
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
Section 16 Synchronous Serial Communication Unit (SSU)
When one byte of the next reception is completed
with RDRF = 1 (except during slave data reception
in SSU mode)
When writing 0 after reading ORER = 1
R
4
0
-
TEND
R/W
3
0
Rev. 3.00 Sep. 28, 2009 Page 801 of 1650
TDRE
R/W
2
1
RDRF
R/W
1
0
R/W
CE
0
0
REJ09B0313-0300