R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 865

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

The I
interface functions. However, the configuration of the registers that control the I
partly from the Philips register configuration.
The I
17.1
• Selection of I
• Continuous transmission/reception
I
• Start and stop conditions generated automatically in master mode
• Selection of acknowledge output levels when receiving
• Automatic loading of acknowledge bit when transmitting
• Bit synchronization function
• Six interrupt sources
• The direct memory access controller (DMAC) can be activated by a transmit-data-empty
• Direct bus drive
Clocked synchronous serial format:
• Four interrupt sources
• The direct memory access controller (DMAC) can be activated by a transmit-data-empty
2
C bus format:
Since the shift register, transmit data register, and receive data register are independent from
each other, the continuous transmission/reception can be performed.
In master mode, the state of SCL is monitored per bit, and the timing is synchronized
automatically. If transmission/reception is not yet possible, set the SCL to low until
preparations are completed.
Transmit data empty (including slave-address match), transmit end, receive data full (including
slave-address match), arbitration lost, NACK detection, and stop condition detection
request or receive-data-full request to transfer data.
Two pins, SCL and SDA pins, function as NMOS open-drain outputs when the bus drive
function is selected.
Transmit-data-empty, transmit-end, receive-data-full, and overrun error
request or receive-data-full request to transfer data.
2
2
C bus interface 3 conforms to and provides a subset of the Philips I
C bus interface 3 has four channels.
Features
2
C format or clocked synchronous serial format
Section 17 I
2
C Bus Interface 3 (IIC3)
Rev. 3.00 Sep. 28, 2009 Page 833 of 1650
Section 17 I
2
C (Inter-IC) bus
2
C Bus Interface 3 (IIC3)
2
C bus differs
REJ09B0313-0300