R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 874

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 17 I
17.3.3
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the transfer bit count.
Bits BC[2:0] are initialized to H'0 by the IICRST bit in ICCR2.
Rev. 3.00 Sep. 28, 2009 Page 842 of 1650
REJ09B0313-0300
Bit
7
6
5, 4
3
I
2
Bit Name
MLS
⎯
⎯
BCWP
C Bus Mode Register (ICMR)
2
C Bus Interface 3 (IIC3)
Initial value:
Initial
Value
0
0
All 1
1
R/W:
Bit:
R/W
MLS
7
0
R/W
R/W
R
R
R/W
R
6
0
-
Description
MSB-First/LSB-First Select
0: MSB-first
1: LSB-first
Set this bit to 0 when the I
Reserved
This bit is always read as 0. The write value should
always be 0.
Reserved
These bits are always read as 1. The write value should
always be 1.
BC Write Protect
Controls the BC[2:0] modifications. When modifying the
BC[2:0] bits, this bit should be cleared to 0. In clocked
synchronous serial mode, the BC[2:0] bits should not
be modified.
0: When writing, values of the BC[2:0] bits are set.
1: When reading, 1 is always read.
R
5
1
-
When writing, settings of the BC[2:0] bits are invalid.
R
4
1
-
BCWP
R/W
3
1
R/W
2
0
BC[2:0]
R/W
1
0
2
C bus format is used.
R/W
0
0