R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 881

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

17.3.6
SAR is an 8-bit readable/writable register that selects the communications format and sets the
slave address. In slave mode with the I
upper seven bits of the first frame received after a start condition, this module operates as the slave
device.
17.3.7
ICDRT is an 8-bit readable/writable register that stores the transmit data. When ICDRT detects the
space in the shift register (ICDRS), it transfers the transmit data which is written in ICDRT to
ICDRS and starts transferring data. If the next transfer data is written to ICDRT while transferring
data of ICDRS, continuous transfer is possible.
Bit
7 to 1
0
Slave Address Register (SAR)
I
2
Bit Name
SVA[6:0]
FS
C Bus Transmit Data Register (ICDRT)
Initial value:
Initial value:
R/W:
R/W:
Initial
Value
0000000
0
Bit:
Bit:
R/W
R/W
7
0
7
1
R/W
R/W
R/W
R/W
R/W
2
C bus format, if the upper seven bits of SAR match the
6
0
6
1
R/W
R/W
5
0
5
1
Description
Slave Address
These bits set a unique address in these bits,
differing form the addresses of other slave devices
connected to the I
Format Select
0: I
1: Clocked synchronous serial format is selected
SVA[6:0]
2
R/W
R/W
C bus format is selected
4
0
4
1
R/W
R/W
3
0
3
1
Rev. 3.00 Sep. 28, 2009 Page 849 of 1650
R/W
R/W
2
0
2
1
2
C bus.
Section 17 I
R/W
R/W
1
0
1
1
R/W
R/W
FS
0
0
0
1
2
C Bus Interface 3 (IIC3)
REJ09B0313-0300