R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 917

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Bit
6 to 4
3
2
1
0
Bit Name
CKDV[2:0]
MUEN
⎯
TRMD
EN
Initial
Value
000
0
0
0
0
R/W
R/W
R/W
R
R/W
R/W
Note:
Note: When mute is enabled, the serial data to be output
Description
Serial Oversampling Clock Division Ratio
Sets the ratio between oversampling clock* and the
serial bit clock. When the SCKD bit is 0, the setting of
these bits is ignored. The serial bit clock is used in the
shift register and is supplied from the SSISCK pin.
000: Serial bit clock frequency = Oversampling clock Frequency/1
001: Serial bit clock frequency = Oversampling clock frequency/2
010: Serial bit clock frequency = Oversampling clock frequency/4
011: Serial bit clock frequency = Oversampling clock frequency/8
100: Serial bit clock frequency = Oversampling clock frequency/16
101: Serial bit clock frequency = Oversampling clock frequency/6
110: Serial bit clock frequency = Oversampling clock frequency/12
111: Setting prohibited
Mute Enable
0: Module is not muted.
1: Module is muted.
Reserved
The read value is undefined. The write value should
always be 0.
Transmit/Receive Mode Select
0: Module is in receive mode.
1: Module is in transmit mode.
SSI Module Enable
0: Module is disabled.
1: Module is enabled.
is replaced with zeros, but data transfer within the
module does not stop. Therefore, dummy data
must be written to SSITRD to prevent a transmit
underflow from occurring.
* Oversampling clock is selected by the setting
of the SCSR bits in the PFC. For details, see
section 25, Pin Function Controller (PFC).
Rev. 3.00 Sep. 28, 2009 Page 885 of 1650
Section 18 Serial Sound Interface (SSI)
REJ09B0313-0300