R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 92

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 CPU
Rev. 3.00 Sep. 28, 2009 Page 60 of 1650
REJ09B0313-0300
Addressing
Mode
Indexed GBR
indirect
TBR duplicate
indirect with
displacement
PC indirect with
displacement
Instruction
Format
@(R0, GBR) The effective address is the sum of GBR value
@@
(disp:8,
TBR)
@(disp:8,
PC)
Effective Address Calculation
and R0.
The effective address is the sum of TBR value
and an 8-bit displacement (disp). The value of
disp is zero-extended, and is multiplied by 4.
The effective address is the sum of PC value and
an 8-bit displacement (disp). The value of disp is
zero-extended, and is doubled for a word
operation, and quadrupled for a longword
operation. For a longword operation, the lowest
two bits of the PC value are masked.
(zero-extended)
(zero-extended)
H'FFFFFFFC
GBR
R0
disp
disp
TBR
PC
2/4
4
×
&
×
+
+
(for longword)
+
PC & H'FFFFFFFC
GBR + R0
+ disp × 4)
PC + disp × 2
+ disp × 4
+ disp × 4
(TBR
TBR
or
Equation
GBR + R0
Contents of
address (TBR
+ disp × 4)
Word:
PC + disp × 2
Longword:
PC &
H'FFFFFFFC +
disp × 4