R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 952

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 19 Controller Area Network (RCAN-TL1)
The locations not used (between H'000 and H'4F3) are reserved and cannot be accessed.
Rev. 3.00 Sep. 28, 2009 Page 920 of 1650
REJ09B0313-0300
H'000
H'002
H'004
H'006
H'008
H'00A
H'00C
H'020
H'022
H'028
H'02A
H'030
H'032
H'038
H'03A
H'040
H'042
H'048
H'04A
H'050
H'052
H'058
H'05A
H'080
H'082
H'084
H'086
H'088
H'08A
H'08C
H'08E
H'090
H'092
H'094
H'096
H'098
H'09A
H'09C
H'09E
Reference Trigger Offset Register (RFTROFF)
Unread Message Status Register (UMSR1)
Unread Message Status Register (UMSR0)
Timer Compare Match Register 0 (TCMR0)
Timer Compare Match Register 1 (TCMR1)
Transmit Acknowledge Register (TXACK1)
Transmit Acknowledge Register (TXACK0)
Mailbox Interrupt Mask Register (MBIMR1)
Mailbox Interrupt Mask Register (MBIMR0)
Remote Frame Pending Register (RFPR1)
Remote Frame Pending Register (RFPR0)
Bit 15
Timer Trigger Control Register0 (TTCR0)
Abort Acknowledge Register (ABACK1)
Abort Acknowledge Register (ABACK0)
Transmit Error
Counter (TEC)
Receive Pending Register (RXPR1)
Receive Pending Register (RXPR0)
Transmit Pending Register (TXPR1)
Transmit Pending Register (TXPR0)
Cycle Maximum/Tx-Enable Window
Bit Configuration Register 1 (BCR1)
Bit Configuration Register 0 (BCR0)
Transmit Cancel Register (TXCR1)
Transmit Cancel Register (TXCR0)
Reference Mark Register (RFMK)
Timer Counter Register (TCNTR)
Interrupt Request Register (IRR)
Master Control Register (MCR)
General Status Register(GSR)
Cycle Counter Register (CCR)
Cycle Time Register (CYCTR)
Interrupt Mask Register (IMR)
Timer Status Register (TSR)
Register (CMAX_TEW)
Figure 19.2 RCAN-TL1 Memory Map
Counter (REC)
Receive Error
Bit 0
H'0A0
H'0A4
H'100
H'104
H'108
H'10A
H'10C
H'10E
H'110
H'120
H'140
H'160
H'2E0
H'300
H'4A0
H'4C0
H'4E0
Tx-Trigger Time Selection Register (TTTSEL)
Timer Compare Match Register 2 (TCMR2)
Mailbox-0 Control 1 (NMC, MBC, DLC)
Mailbox-1 Control/LAFM/Data etc.
Mailbox-3 Control/LAFM/Data etc.
Mailbox-2 Control/LAFM/Data etc.
Mailbox-15 Control/LAFM/Data etc.
Mailbox-16 Control/LAFM/Data etc.
Mailbox-29 Control/LAFM/Data etc.
Mailbox-30 Control/LAFM/Data etc.
Mailbox-31 Control/LAFM/Data etc.
0
2
4
6
Mailbox 0 Data (8 bytes)
(StdID, ExtID, Rtr, Ide)
Mailbox-0 Control 0
Timestamp
LAFM
1
3
5
7