R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 953

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

19.3.2
Mailboxes play a role as message buffers to transmit/receive CAN frames. Each Mailbox is
comprised of 3 identical storage fields that are 1): Message Control, 2): Local Acceptance Filter
Mask, 3): Message Data. In addition some Mailboxes contain the following extra Fields: 4): Time
Stamp, 5): Time Trigger configuration and 6): Time Trigger Control. The following table shows
the address map for the control, LAFM, data, timestamp, Transmission Trigger Time and Time
Trigger Control addresses for each mailbox.
Mailbox 4 bytes
0
(Receive
Only)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Mailbox Structure
Control0
100 – 103
120 – 123
140 – 143
160 – 163
180 – 183
1A0 – 1A3 1A4 – 1A7 1A8 – 1AF 1B0 – 1B1 1B2 – 1B3 No
1C0 – 1C3 1C4 – 1C7 1C8 – 1CF 1D0 – 1D1 1D2 – 1D3 No
1E0 – 1E3 1E4 – 1E7 1E8 – 1EF 1F0 – 1F1
200 – 203
220 – 223
240 – 243
260 – 263
280 – 283
2A0 – 2A3 2A4 – 2A7 2A8 – 2AF 2B0 – 2B1 2B2 – 2B3 No
2C0 – 2C3 2C4 – 2C7 2C8 – 2CF 2D0 – 2D1 2D2 – 2D3 No
2E0 – 2E3 2E4 – 2E7 2E8 – 2EF 2F0 – 2F1
300 – 303
320 – 323
340 – 343
LAFM
4 bytes
104– 107
124 – 127
144 – 147
164 - 167
184 – 187
204 – 207
224 – 227
244 – 247
264 – 267
284 – 287
304 – 307
324 – 327
344 – 347
Data
8 bytes
108 – 10F
128 – 12F
148 – 14F
168 – 16F
188 – 18F
208 – 20F
228 – 22F
248 – 24F
268 – 26F
288 – 28F
308 – 30F
328 – 32F
348 – 34F
2 bytes
Control1
110 – 111
130 – 131
150 – 151
170 – 171
190 – 191
210 – 211
230 – 231
250 – 251
270 – 271
290 – 291
310 – 311
330 – 331
350 – 351
Address
Section 19 Controller Area Network (RCAN-TL1)
Rev. 3.00 Sep. 28, 2009 Page 921 of 1650
Time
Stamp
2 bytes
112 – 113
132 – 133
152 – 153
172 – 173
192 – 193
1F2 – 1F3
212 – 213
232 – 233
252 – 253
272 – 273
292 – 293
2F2 – 2F3
No
No
No
Trigger
Time
2 bytes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
REJ09B0313-0300
TT control
2 bytes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No
No