R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 957

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Notes: 1. All bits shadowed in grey are reserved and must be written LOW. The value returned
MB30 (Time Reference Transmitssion in Time Trigger mode)
H'10A + N*32
H'10C + N*32
H'10E + N*32
H'10A + N*32
H'10C + N*32
H'10E + N*32
H'100 + N*32
H'102 + N*32
H'104 + N*32
H'106 + N*32
H'108 + N*32
H'100 + N*32
H'102 + N*32
H'104 + N*32
H'106 + N*32
H'108 + N*32
H'110 + N*32
H'112 + N*32
H'114 + N*32
H'110 + N*32
H'112 + N*32
MB31 (Time Reference Reception in Time Trigger mode)
Address
Address
2. ATX and DART are not supported by Mailbox-0, and the MBC setting of Mailbox-0 is
3. ID Reorder (MCR15) can change the order of STDID, RTR, IDE and EXTID of both
LAFM
LAFM
IDE_
IDE_
IDE
IDE
15
15
by a read may not always be ‘0’ and should not be relied upon.
limited.
message control and LAFM.
0
0
RTR
RTR
14
14
0
0
0
0
MSG_DATA_0 (first Rx/Tx Byte)
MSG_DATA_0 (first Rx/Tx Byte)
NMC
NMC
13
13
0
0
0
0
MSG_DATA_2
MSG_DATA_4
MSG_DATA_6
MSG_DATA_2
MSG_DATA_4
MSG_DATA_6
ATX DART
ATX DART
12
12
Figure 19.3 Mailbox-N Structure (continued)
11
11
Tx-Triggered Time (TTT) as Time Reference
10
TimeStamp[15:0] (TCNTR at SOF)
10
TimeStamp[15:0] (TCNTR at SOF)
MBC[2:0]
MBC[2:0]
STDID_LAFM[10:0]
9
9
STDID_LAFM[10:0]
EXTID_LAFM[15:0]
EXTID_LAFM[15:0]
STDID[10:0]
STDID[10:0]
EXTID[15:0]
EXTID[15:0]
Data Bus
Data Bus
8
8
7
0
7
0
6
0
6
0
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
MSG_DATA_7
MSG_DATA_1
MSG_DATA_3
MSG_DATA_5
MSG_DATA_7
5
0
5
0
Section 19 Controller Area Network (RCAN-TL1)
4
0
4
0
3
3
Rev. 3.00 Sep. 28, 2009 Page 925 of 1650
DLC[3:0]
DLC[3:0]
2
2
EXTID[17:16]
EXTID[17:16]
LAFM[17:16]
LAFM[17:16]
1
1
EXTID_
EXTID_
0
0
Byte/Word/LW
Byte/Word/LW
Byte/Word/LW
Byte/Word/LW
Access Size
Access Size
Byte/Word
Byte/Word
Byte/Word
Byte/Word
Byte/Word
Byte/Word
Word/LW
Word/LW
Word/LW
Word/LW
Word
Word
Word
Word
Word
Word
Word
REJ09B0313-0300
Trigger Time
TimeStamp
TimeStamp
Field Name
Field Name
Control 0
Control 1
Control 1
Control 0
LAFM
LAFM
Data
Data