R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 959

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

• Mailbox-0
Note: MBC[1] of MB0 is always "1".
• Mailbox-31 to 1
NMC (New Message Control): When this bit is set to ‘0’, the Mailbox of which the RXPR or
RFPR bit is already set does not store the new message but maintains the old one and sets the
UMSR correspondent bit. When this bit is set to ‘1’, the Mailbox of which the RXPR or RFPR bit
is already set overwrites with the new message and sets the UMSR correspondent bit.
Important: Please note that if a remote frame is overwritten with a data frame or vice versa could
be that both RXPR and RFPR flags (together with UMSR) are set for the same Mailbox. In this
case the RTR bit within the Mailbox Control Field should be relied upon.
Important: Please note that when the Time Triggered mode is used NMC needs to be set to ‘1’
for Mailbox 31 to allow synchronization with all incoming reference messages even when
RXPR[31] is not cleared.
NMC
0
1
Initial value:
Initial value:
R/W:
R/W:
Bit:
Bit:
15
15
R
R
0
0
0
0
Description
Overrun mode (Initial value)
Overwrite mode
14
14
R
R
0
0
0
0
NMC
R/W
NMC
R/W
13
13
0
0
R/W
ATX
12
12
R
0
0
0
DART
R/W
11
11
R
0
0
0
R/W
R/W
10
10
1
1
MBC[2:0]
MBC[2:0]
R/W
R
9
1
9
1
R/W
R/W
8
1
8
1
Section 19 Controller Area Network (RCAN-TL1)
R
7
0
R
0
7
0
0
Rev. 3.00 Sep. 28, 2009 Page 927 of 1650
R
6
0
R
0
6
0
0
R
5
0
R
0
5
0
0
R
4
0
R
0
4
0
0
R/W
R/W
3
0
3
0
R/W
R/W
REJ09B0313-0300
2
0
2
0
DLC[3:0]
DLC[3:0]
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0