R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 965

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Important: Please note that the TimeStamp is stored in a temporary register. Only after a
successful transmission or reception the value is then copied into the related Mailbox field. The
TimeStamp may also be updated if the CPU clears RXPR[N]/RFPR[N] at the same time that
UMSR[N] is set in overrun, however it can be read properly before clearing RXPR[N]/RFPR[N].
(5)
For Mailbox-29 to 24, when MBC is set to 000 (Bin) in time trigger mode (CMAX!= 3'b111), Tx-
Trigger Time works as Time_Mark to determine the boundary between time windows. The TTT
and TT control are comprised of two 16-bit read/write areas as follows. Mailbox-30 doesn't have
TT control and works as Time_Ref.
Mailbox 30 to 24 can be used for reception if not used for transmission in TT mode. However they
cannot join the event trigger transmission queue when the TT mode is used.
• Tx-Trigger Time
Initial value:
• Time Trigger control
Initial value:
The following figure shows the differences between all Mailboxes supporting Time Triggered
mode.
R/W:
R/W:
Tx-Trigger Time (TTT) and Time Trigger control
Bit:
Bit:
TTT15 TTT14 TTT13 TTT12 TTT11
R/W
R/W
15
15
0
0
TTW[1:0]
R/W
R/W
14
14
0
0
R/W
R/W
13
13
0
0
R/W
R/W
12
12
0
0
R/W
R/W
11
11
0
0
Offset[5:0]
TTT10
R/W
R/W
10
10
0
0
TTT9
R/W
R/W
9
0
9
0
TTT8
R/W
R/W
8
0
8
0
Section 19 Controller Area Network (RCAN-TL1)
TTT7
R/W
7
0
R
7
0
0
Rev. 3.00 Sep. 28, 2009 Page 933 of 1650
TTT6
R/W
6
0
R
6
0
0
TTT5
R/W
5
0
R
5
0
0
TTT4
R/W
4
0
R
4
0
0
TTT3
R/W
3
0
R
3
0
0
REJ09B0313-0300
TTT2
R/W
R/W
2
0
2
0
rep_factor[2:0]
TTT1
R/W
R/W
1
0
1
0
TTT0
R/W
R/W
0
0
0
0