R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 993

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

(1)
The concatenation of TXPR1 and TXPR0 is a 32-bit register that contains any transmit pending
flags for the CAN module. In the case of 16-bit bus interface, Long Word access is carried out as
two consecutive word accesses.
<Longword Write Operation>
<Longword Read Operation>
The TXPR1 controls Mailbox-31 to Mailbox-16, and the TXPR0 controls Mailbox-15 to Mailbox-
1. The CPU may set the TXPR bits to affect any message being considered for transmission by
writing a ‘1’ to the corresponding bit location. Writing a ‘0’ has no effect, and TXPR cannot be
cleared by writing a ‘0’ and must be cleared by setting the corresponding TXCR bits. TXPR may
be read by the CPU to determine which, if any, transmissions are pending or in progress. In effect
there is a transmit pending bit for all Mailboxes except for the Mailbox-0. Writing a ‘1’ to a bit
location when the mailbox is not configured to transmit is not allowed.
Transmit Pending Register (TXPR1, TXPR0)
Data is stored into Temp instead of TXPR1.
TXPR0 is stored into Temp,
when TXPR1 is read.
TXPR1
Temp
H'020
TXPR1
H'020
16-bit Peripheral bus
<upper word write>
16-bit Peripheral bus
<upper word read>
TXPR0
H'022
TXPR0
Temp
H'022
consecutive access
consecutive access
Section 19 Controller Area Network (RCAN-TL1)
Temp is read instead of TXPR0.
Longword data are stored into
both TXPR1 and TXPR0 at the same time.
Rev. 3.00 Sep. 28, 2009 Page 961 of 1650
TXPR1
Temp
H'020
TXPR1
H'020
16-bit Peripheral bus
<lower word write>
16-bit Peripheral bus
<lower word read>
TXPR0
H'022
TXPR0
Temp
H'022
REJ09B0313-0300