R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 129
R5S72030W200FP
Manufacturer Part Number
R5S72030W200FP
Description
IC SUPERH MPU ROMLESS 240QFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH7200r
Specifications of R5S72030W200FP
Core Processor
SH2A-FPU
Core Size
32-Bit
Speed
200MHz
Connectivity
CAN, I²C, SCI, SSI, SSU, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
82
Program Memory Type
ROMless
Ram Size
80K x 8
Voltage - Supply (vcc/vdd)
1.1 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
240-QFP
For Use With
R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5S72030W200FP
Manufacturer:
SAMSUNG
Quantity:
1 001
Company:
Part Number:
R5S72030W200FP
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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6.3.13
Format
DIVS R0,Rn
Description
Executes division of the 32-bit contents of a general register Rn (dividend) by the contents of R0
(divisor). This instruction executes signed division and finds the quotient only. A remainder
operation is not provided. To obtain the remainder, find the product of the divisor and the
obtained quotient, and subtract this value from the dividend. The sign of the remainder will be the
same as that of the dividend.
Notes
An overflow exception will occur if the negative maximum value (H'00000000) is divided by –1.
If division by zero is performed a division by zero exception will occur.
If an interrupt is generated while this instruction is being executed, execution will be halted. The
return address will be the start address of this instruction, and this instruction will be re-executed.
Operation
Examples:
DIVS
{
}
DIVS R0,R1
R[n]=R[n] / R[0];
PC+=2;
DIVS
Signed Division
(long n)
Abstract
Signed, Rn ÷ R0 → Rn
/*
; R1(32bits) / R0 (32bits) = R1(32bits); signed
DIVS
DIVide as Signed
R0, Rn */
Rev. 3.00 Jul 08, 2005 page 113 of 484
Code
0100nnnn10010100
Section 6 Instruction Descriptions
Arithmetic Instruction
SH-2A/SH2A-FPU (New)
REJ09B0051-0300
Cycle
36
T Bit
―
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