R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 17

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

1.1
The SH-2A/SH2A-FPU is a 32-bit RISC (reduced instruction set computer) microprocessor that is
upward-compatible with the SH-1, SH-2, and SH-2E at the object code level. The SH2A-FPU has
an on-chip floating point unit and the SH-2A does not. The use of 16-bit basic instructions enables
code efficiency, performance, and ease of use to be improved.
Features of the SH-2A/SH2A-FPU are summarized in table 1.1.
Table 1.1
Item
CPU
Features
SH-2A/SH2A-FPU Features
Features
•
•
•
•
•
•
•
•
•
•
Original Renesas Technology architecture
32-bit internal data bus
General-register architecture
 Sixteen 32-bit general registers
 Four 32-bit control registers
 Four 32-bit system registers
 Register banks for fast interrupt response
RISC-type instruction set (upward-compatible with SH Series)
 Instruction length: 16-bit basic instructions for improved efficiency,
 Load-store architecture
 Delayed branch instructions
 Instruction set based on C language
Superscalar architecture allowing simultaneous execution of two
instructions, including FPU
Instruction execution time: Max. 2 instructions/cycle
Address space: 4 Gbytes
On-chip multiplier
Five-stage pipeline
Harvard architecture
and 32-bit instructions for improved performance and ease of use
Section 1 Overview
Rev. 3.00 Jul 08, 2005 page 1 of 484
Section 1 Overview
REJ09B0051-0300