R5S72030W200FP Renesas Electronics America, R5S72030W200FP Datasheet - Page 30

• Manufacturer Part Number: R5S72030W200FP
• Description: IC SUPERH MPU ROMLESS 240QFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7200r

Specifications of R5S72030W200FP

• Core Processor: SH2A-FPU
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: CAN, I²C, SCI, SSI, SSU, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 82
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.1 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 240-QFP
• For Use With: R0K572030S000BE - KIT DEV FOR SH7203HS0005KCU11H - EMULATOR E10A-USB H8S(X),SH2(A)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -

Section 2 Programming Model
(1) Reset State
In this state, the CPU is reset. There are two kinds of reset, power-on and manual. See the
Hardware Manual for details.
(2) Exception Handling State
The exception handling state is a transient state that occurs when the CPU alters the normal
programming flow due to a reset, interrupt, or other exception handling source.
In the case of a reset, the CPU fetches the execution start address as the initial value of the
program counter (PC) from the exception vector table, and the initial value of the stack pointer
(SP), stores these values, branches to the start address, and begins program execution at that
address.
In the case of an interrupt, etc., the CPU references the SP and saves the PC and status register
(SR) in the stack area. It fetches the start address of the exception service routine from the
exception vector table, branches to that address, and begins program execution.
Subsequently, the processing state is the program execution state.
(3) Program Execution State
In the program execution state the CPU executes program instructions in the normal sequence.
(4) Power-Down State
In the power-down state the CPU stops operating to conserve power. Sleep mode or software
standby mode is entered by executing a SLEEP instruction. If hardware standby input is received,
the CPU enters the hardware standby mode.
(5) Bus-Released State
In the bus-released state, the CPU releases the bus to a device that has requested it.
Note: For information on the processing states, please refer to the hardware manual for the
product in question.
Rev. 3.00 Jul 08, 2005 page 14 of 484
REJ09B0051-0300